The present invention relates, in general, to the field of integrated circuit (IC) memory devices. More particularly, the present invention is related to a twin cell architecture for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM.
Power is a large concern for today's integrated circuit memory devices. Many present day applications are mobile, and extended battery life can provide a key market advantage. Nevertheless, for applications that are not battery powered, power is also important. Power consumption leading to device heating problems can add extra expense to systems in the way of cooling fans or larger heat sinks. High power consumption in memory circuits may also require the system to operate at reduced clock frequencies.
Radiation hardness is a reliability problem for semiconductor integrated circuits. Military, space and consumer applications all require low failure rate levels. If failures due to radiation are too high in consumer products, additional expenses are incurred in implementing error correction code (ECC) logic or additional ECC capability. If failure rates due to radiation effects are too high for governmental applications, typically after ECC has already been employed, the product will be rejected for such an application.
For network, internet, gaming and other applications, random access cycle time (or the tRC specification for DRAMs) is desired to be minimized. Historically, static random access memory devices (SRAMs) have a large advantage over DRAMs in providing this type of device performance. What is needed then is a memory circuit with the higher density of DRAM memories in conjunction with the faster random cycle time performance of SRAM memories.
It is also known that grounded bitline precharge designs require complicated reference voltage circuitry. For certain very low voltage applications, grounded bitline, or supply voltage level (e.g. VCC) bitline precharge, designs are required for DRAM memory arrays. These non-VCC/2 bitline precharge designs require a reference voltage that is challenging to generate for reliable bitline sensing.
DRAM memory circuits are generally optimized on a cost per bit basis. This cost may be minimized by minimizing the DRAM memory cell footprint. Most DRAM manufacturers are currently implementing a cell that is referred to as an 8F squared cell, or 8F2, where F represents the minimum photolithography feature size for a given technology node. For example, at the 70 nm design node, a memory cell may be 8×70n2 or 0.0392 square microns in size. Some advanced memory cell technologies have the capability to utilize 6F squared memory cells. In the foregoing example, a 6F squared (6F2) cell can be implemented in an area of 0.0294 square microns. Most 6F2 DRAM cells require open bitline architectures as opposed to the well known folded bitline sub-array architecture. Nevertheless, conventional open bitline sub-arrays can be inefficient and prone to noise related problems.